1. Field of the Invention
This invention relates to the testing of digital logic arrays of the type useful in digital computer systems, and particularly to methods of providing built-in automatic testing of such arrays without removing them from the systems of which they are part.
2. Description of the Prior Art
References:
Application Articles on Signature Analysis, 1979, Hewlett-Packard Application Note #222-2, Hewlett-Packard Publication 5952-7542. PA1 Williams, T. and Parker, K., "Design for Testability--A Survey", IEEE Transactions on Computers, January 1982.
Logic arrays are networks of logic circuits (AND gates, OR gates, flip-flops, and the like) that perform some logical function (e.g., instruction decoding, interrupt dispatching). Digital data systems and digital computers generally comprise interconnected logic arrays.
Recent developments in integrated circuit technology have enabled whole arrays to be packaged as single entities; this in turn has made it desirable to be able to comprehensively test the entity without removing it from the system of which it is a part. Such a test need only indicate whether the array as a whole is functional, and need not diagnose the nature of malfunctions since the usual remedy is to replace the entire entity.
Considerable work has been done relating to methods of self-testing logic arrays. One possible method involves a GO/NO-GO type test that can be executed automatically upon power-up or at any time by asserting a control line on the array to the appropriate state, which results in applying an input pattern to the array and verifying that the output pattern is as expected. This method has limitations; the limited number of input patterns that may be produced as a result of asserting a single control line may not represent a comprehesive test of the array and thus many failures may go undetected. The GO/NO-GO type test can be applied to any logic array, but it is expensive to implement on a highly combinatorial array; highly combinatorial arrays (as opposed to highly registered arrays) require the addition of hardware at the inputs and outputs to buffer the requisite data patterns. This additional hardware consumes array cells. Arrays that are highly registered only require additional hardware to adapt the registers to be more amenable to self-testing. This consumes cells, but not as many as those consumed for a combinatorial type.
Another method, known as SCAN, involves extracting out stored data from within the array during a procedure specifically targeted toward analyzing the extracted data in order to diagnose a problem. A drawback of this method is that the amount of prestored data is inherently limited, and may not represent a sufficient number of patterns to comprehensively test the array, resulting in undetected failures. And, the SCAN method does not apply to highly combinatorial arrays because there is little or no internally registered data; this method better lends itself to highly registered arrays.
Other methods involve the use of external intelligence to generate data patterns and input them to the array under test, and the use of other external intelligence to receive and analyze the outputs. Such methods may be effective, but one of their drawbacks is that they are time-consuming. And the required external intelligence takes them out of the self-test category anyway.
Another previously known self-test method employs a register at the inputs to a logic array and a similar register at the outputs. These registers are used to generate pseudorandom patterns that propagate through the array and generate a set of patterns specific to the array. These patterns can be captured and compressed using signature analysis methodology to generate a single word that characterizes the array relative to the stimulating patterns. This method has the acronym "BILBO", derived from "Built-In Logic Block Observer". If this resultant word is EXCLUSIVE OR'ed with an internally stored expected result, a single GO/NO-GO indication can be generated.
Logic simulation techniques were employed to evaluate a BILBO implementation with a typical logic array (an instruction decoder). The BILBO methodology was found to provide an effective self-test of the array, but a major disadvantage related to the amount of circuitry necessary to implement the test, which consumed roughly one-third of the cells comprising the array. This was deemed to be excessive, and applicants sought a way of providing an adequate self-test mechanism that would not add so much circuitry overhead.
An adaptation of BILBO that was investigated was to "team" two arrays and two BILBO registers in such a manner that when one array is to be tested the first register provides its input and the second register collects its output, and when the second array is to be tested the second register provides its input and the first register collects its output. While this approach does effect some reduction in circuitry overhead, it was not quite a 50% reduction since added complexity is introduced in order to configure for the different modes of testing. Another significant drawback of this approach is that constraints are introduced on the physical placement of the two arrays relative to each other, since they must now interact in ways that would be unnecessary but for the added self-testing feature.